Skip to Main Content
Design strategies for power effective and high resolution successive-approximation ADCs for autonomous multi-sensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si test-chip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1 muW power consumption on a 1.2-V supply. The achieved Figure-of-Merit is 165 fJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14 mum CMOS technology with only three metal layers.