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Concurrent logic and layout design system for high performance LSIs

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7 Author(s)
Murakata, M. ; ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan ; Murofushi, M. ; Igarashi, M. ; Aoki, T.
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This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995

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