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A high-speed, high-resolution analog front end for digital subscriber line applications

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8 Author(s)

A 5 V CMOS chip providing the D/A, A/D, filter, and a programmable gain amplifier (PGA) for HDSL and ADSL is described. The chip includes 12-bit, 10 Msample/sec converters, filters, and a PGA having 48 dB gain with 1.7 MHz bandwidth. This chip is used in an E1-rate (2.048 Mbps) ADSL transceiver achieving a bit error rate of less than 10-9 over 5.4 km of 0.4 mm twisted copper wire

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995

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