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Optimal and efficient buffer insertion and wire sizing

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3 Author(s)
Lillis, J. ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA ; Chung-Kuan Cheng ; Lin, T.T.Y.

We present optimal solutions to the following problems: (1) post-layout buffer insertion, (2) wire-sizing and (3) simultaneous buffer insertion and wire-sizing. We optimize a practical objective function: required arrival time. To the best of our knowledge, this work represents the first sub-exponential algorithms for these problems. In experiments, we observe substantial improvements over previous results for buffer insertion, and up to 25% improvement in delay by wire-sizing

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995

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