Cart (Loading....) | Create Account
Close category search window

The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
El-Desouki, M.M. ; Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada ; Abdelsayed, S.M. ; Deen, M.J. ; Nikolova, N.K.
more authors

Achieving power- and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of power-efficient CMOS radio-frequency integrated circuits (RF ICs). In addition, the parasitics of on-chip passive components that are integrated on lossy silicon substrates have made CMOS-based integrated circuits inferior to their compound-semiconductor counterparts. The parasitic effects of on-chip interconnections play a key role in RF circuit performance, particularly as the frequency of operation increases. Neglecting these effects leads to the significant degradation in circuit performance or even failure of operation in some cases. Furthermore, unlike transistors, miniaturization of interconnections does not improve their performance. This paper demonstrates the impact of metal layer resistivity and layout parasitics on an RF power amplifier (PA) and a low-noise amplifier (LNA). A nonlinear fully integrated 2.4-GHz class-E PA, with a class-F driver stage, and a 5-GHz LNA are discussed. The circuits were fabricated in a standard 0.18- mum CMOS technology. The layouts of the presented CMOS amplifiers were designed by carefully modeling the interconnection wires during the simulations and optimizing their widths for minimum parasitic effects and hence optimum measured circuit performance. Due to the careful layout design and interconnection optimization, the implemented amplifier circuits showed a good match between the measured and simulated performance characteristics.

Published in:

Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 9 )

Date of Publication:

Sept. 2009

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.