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Random telegraph signal (RTS) noise is of increasing concern for sub-100-nm flash memories. To quantitatively study the shallow trench isolation (STI) edge effect, NMOS devices with and without STI edges in the channel area are designed and analyzed. The significant impact of STI on width scaling is demonstrated and quantified. It is shown that the noise induced by STI edges dominates the RTS noise for smaller device sizes and is caused by an increase in the number of trapping sites at the STI edges. By rounding the STI corner, the number of stress-induced traps can be significantly reduced.