Skip to Main Content
This paper presents two efficient decoder designs for the low-density parity-check codes in IEEE 802.15.3 standard proposal. These decoders feature by efficient hardware usage, low message memory requirement and code rate flexibility. The highly parallel level design can reach a throughput of 3.6 Gbps, which fulfills the standard requirement by processing 72 columns and 72 rows in parallel. The low cost design offers another tradeoff which significantly reduces the area and power consumption while maintaining necessary data throughput required by specific applications. Furthermore, both decoders support three different code rates by employing flexible check node processing units.