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A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

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3 Author(s)
Yeong-Kang Lai ; Dept. of the Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan ; Lien-Fei Chen ; Yui-Chih Shih

In this paper, we present a high performance and memory-efficient pipelined architecture with parallel scanning method for 2-D lifting-based DWT in JPEG2000 applications. The Proposed 2-D DWT architecture are composed of two 1-D DWT cores and a 2times2 transposing register array. The proposed 1-D DWT core consumes two input data and produces two output coefficients per cycle, and its critical path takes one multiplier delay only. Moreover, we utilize the parallel scanning method to reduce the internal buffer size instead of the line-based scanning method. For the NtimesN tile image with one-level 2-D DWT decomposition, only 4N temporal memory and the 2times2 register array are required for 9/7 filter to store the intermediate coefficients in the column 1-D DWT core. And the column-processed data can be rearranged in the transposing array. According to the comparison results, the hardware cost of the 1-D DWT core and the internal memory requirements of proposed 2-D DWT architecture are smaller than other familiar architectures based on the same throughput rate. The implementation results show that the proposed 2-D DWT architecture can process 1080 p HDTV pictures with five-level decomposition at 30 frames/sec.

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Consumer Electronics, IEEE Transactions on  (Volume:55 ,  Issue: 2 )