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Signal processing has been implemented in many computing devices that are successfully being used in mission-critical NASA programs, military operations, and medical devices. The popularity and demand of signal processing systems are increasing in many other domains including commercial products. Many applications in signal processing systems need tremendous amount of processing speed. In addition to efficient algorithms, signal processing systems need the best hardware support to deliver the required level of performance. Most high-performance processing cores consume l dissipate significant amount of energy challenging the (battery-life l) cooling system. It has been established that cache memory has strong influence on the performance and energy consumption of data and computation intensive systems. In this work, we model a signal processing system with a single core and a two-level cache memory hierarchy and simulate the model using MPEG-4 and H.264/AVC encoding algorithms in order to optimize the performance and energy consumption by varying the level-2 cache attributes. Simulation results indicate that tuning cache memory attributes can improve the performance and decrease the energy consumption of a given signal processing architecture. Results also indicate that this simulation platform can be used to select the right signal processing algorithm for a given architecture at an earlier stage of the design process.