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This paper describes a quantization noise reduction method in DeltaSigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. Combined with the hybrid FIR filtering, single-loop topology makes 4th-order and 5th-order DeltaSigma modulators possible for the type-2 4th-order PLL. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.