By Topic

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hossain, M. ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Carusone, A.C.

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 mum digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is -101 dBc/Hz @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 GHz clock while consuming 14 mW in 90 nm CMOS.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 8 )