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A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

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6 Author(s)
Kwang-Il Oh ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Lee-Sup Kim ; Kwang-Il Park ; Young-Hyun Jun
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A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 8 )

Date of Publication:

Aug. 2009

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