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Second-Bit-Effect-Free Multibit-Cell Flash Memory Using \hbox {Si}_{3} \hbox {N}_{4}/\hbox {ZrO}_{2} Split Charge Trapping Layer

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5 Author(s)
Gang Zhang ; SKKU Adv. Inst. of Nanotechnol., Sungkyunkwan Univ., Suwon, South Korea ; Seung-Hwan Lee ; Chang Ho Ra ; Hua-Min Li
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In this paper, a Si3N4/ZrO2 split charge trapping layer (SCTL) is proposed for multibit-cell Flash memory. The complementary potential wells of Si3N4/ZrO2 storage nodes enable independent node control when the Fowler-Nordheim (F-N) method is applied for programming/erasing (P/E). Experiment and simulation results suggest that the 2-bit (2-b) charge storage is accomplished by physical data node separation for the SCTL rather than charge injection control. The well-confined charge storages suppress the second-bit effect, enabling excellent 2-b data clearance for short-channel SCTL devices. It was found that the remaining memory windows after 105 s decrease, dependent on the difference of the trap properties between Si3N4 and ZrO2.

Published in:
Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 9 )

Date of Publication: Sept. 2009

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