By Topic

Performance analysis of parallel FDTD algorithm on different hardware platforms

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wenhua Yu ; Electromagnetic Communication Laboratory, 319 EE East, University Park 16802, USA ; Raj Mittra ; Xiaoling Yang ; Yongjun Liu

Rapid developments in computer techniques and high performance networks have led to the widespread use of the parallel FDTD method for solving large EM problems. It is well known that the FDTD method is an embarrassingly parallel algorithm, which can make an efficient use of a computer cluster to reduce the computation time almost linearly as the number of nodes is increased, provided that the code is structured correctly and is run on the dasiarightpsila platform. In this communication, we investigate the parallel performance of the parallel FDTD method on different hardware platforms.

Published in:

2009 IEEE Antennas and Propagation Society International Symposium

Date of Conference:

1-5 June 2009