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Low Power Design of a Grating Detection System Chip

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3 Author(s)
Li-Gang Hou ; VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China ; Xiao-Hong Peng ; Wu-Chen Wu

This paper forwards a low power design of a grating detection system chip (GDC) on length and angle precision measurement. Traditional grating detection methods are complex, costly, and suffer big power consumption for the complex divide circuit scheme and CPU software compensation. GDC achieves the whole grating detection system function, high speed orthogonal signal handling in a single chip with very low power consumption. It is an application-specific integrated circuit (ASIC), integrated micro controller unit (MCU), power management unit (PMU), two LCD controller, keyboard interface, grating detection unit and other peripherals. Working at 10 MHz, GDC can afford 5 MHz internal sampling rate and 1.25 MHz orthogonal signal from grating sensor. By implementing low power system design, orthogonal signal dividing and Low power divider design, GDC consumes 0.9 mw in test mode and 0.2 mw in real mode. GDC is tape out in HJTC 180 nm process with evaluation kit and demo system developed.

Published in:

Computer Science and Information Engineering, 2009 WRI World Congress on  (Volume:3 )

Date of Conference:

March 31 2009-April 2 2009