By Topic

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Josep Rius ; Dept. Eng. Electron., Univ. Politec. de Catalunya, Barcelona, Spain ; Luis Elvira Villagra ; Maurice Meijer

A novel method to detect a defective IDDQ on top of high background current is proposed. Instead of the conventional approach that measures the quiescent current drawn by the circuit-under-test (CUT), the proposed method is based on the measurement of the voltage drop in a resistor spatially laid-out along the CUT. Resistive shorts with a defective current of 2.14 muA on top of 83.11 muA of leakage current have been detected in a 65 nm CMOS test chip with controllable leakage. The proposed method also provides facilities to locate the defect in addition to detect it.

Published in:

2009 14th IEEE European Test Symposium

Date of Conference:

25-29 May 2009