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A 5-GHz CMOS Type-II PLL With Low K_{\rm VCO} and Extended Fine-Tuning Range

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2 Author(s)
Bruss, S.P. ; Dept. of Electr. & Comput. Eng., Univ. of California at Davis, Davis, CA, USA ; Spencer, R.R.

A 5-GHz dual-path integer-N Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low K VCO of 3.2 MHz/V. The reference spur level is less than -70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is -75 and -115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-mm2 PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.

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Microwave Theory and Techniques, IEEE Transactions on  (Volume:57 ,  Issue: 8 )