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Silicon and Nanoscale Metal Interface Characterization Using Stress-Engineered Superlayer Test Methods

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4 Author(s)
Jiantao Zheng ; Comput.-Aided Simulation of Packaging Reliability (CASPaR) Lab., Georgia Inst. of Technol., Atlanta, GA, USA ; Modi, M. ; Ginga, N. ; Sitaraman, S.

Thin film layers are utilized in emerging microelectronics, optoelectronics, and microelectromechanical systems (MEMS) devices. Typically, these thin film layers are composed of different materials with dissimilar properties. A common mode of failure for thin films is delamination caused by external loading or intrinsic stress present in the materials. To characterize bonded thin film material systems, it is necessary to measure the interfacial fracture toughness. When material thicknesses approach micro- and nanoscales, interfacial fracture toughness measurement is a challenging task. Accordingly, innovative test techniques need to be developed to study interfacial fracture parameters. The ongoing research at Georgia Institute of Technology is developing fixtureless delamination test techniques that can be used to measure interfacial properties of micro- and nanoscale thin films. The single substrate decohesion test (SSuDT) and the single-strip decohesion Test (SSDT) are such fixtureless tests under development. In these tests, a thin film interface material of interest is deposited on a substrate. Then, delamination is driven by a superlayer material on top of the interface material. This superlayer material is sputter deposited and has high intrinsic stress. A deposited release layer material allows for the contact area between the interface material and the substrate to be controlled. These tests differ in geometry, but share the same generic methodology and can be used for a number of material systems over a wide range of mode mixities. This paper presents the methodology and implementation of the SSuDT and SSDT tests and compares results to better understand their scope. A case study of the interfacial fracture toughness as a function of mode mixity for titanium and silicon interface was performed.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:32 ,  Issue: 2 )

Date of Publication:

June 2009

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