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Variation-Tolerant Dynamic Power Management at the System-Level

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4 Author(s)
Chandra, S. ; Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA ; Lahiri, K. ; Raghunathan, A. ; Dey, S.

The power characteristics of system-on-chips (SoCs) in nanoscale technologies are significantly impacted by manufacturing process variations, making it important to consider these effects during system-level power analysis and optimization. In this paper, we identify and address the problem of designing effective power management schemes in the presence of such variations. In particular, we demonstrate that conventional power management schemes, which are designed without considering the impact of variations, can result in substantial power wastage. We therefore propose two approaches to variation-aware power management, namely, design-specific and chip-specific approaches. In each of these approaches, the goal is to consider the impact of variations while deriving power management policy parameters, in order to optimize metrics that are relevant under variations. We motivate and introduce these metrics, and present both exact and heuristic approaches to optimize them. The methods are designed and implemented in the context of two power management frameworks, namely an ideal oracle-based framework and a timeout-based framework. We experimentally evaluate the proposed ideas using an ARM946 processor core model. For the oracle-based framework, variation-aware power management can result in improvements of upto 59% for mu+sigma , and upto 55% for 95th percentile of the energy distribution, over conventional power management schemes that do not consider variations. For the timeout-based framework, we obtain reductions of upto 43% in mu+sigma and upto 55% in the 99th percentile of the energy distribution.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 9 )

Date of Publication:

Sept. 2009

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