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Modulo 2n + 1 multipliers are the primitive computational logic components widely used in residue arithmetic, digital signal processing and cryptography. In this work, a fast low-power hardware implementation of modulo 2n + 1 multiplier is proposed and validated. The proposed hardware architecture is based on the efficient compressors and modulo carry look-ahead adders as the basic building blocks. The modulo carry lookahead adder uses the sparse-tree adder technique to achieve better speed. The resulting implementations are compared both qualitatively and quantitatively, in standard CMOS cell technology, with the existing implementations. The results show that the proposed implementation is considerably faster and consume significantly less power than similar hardware implementations making them a viable option for efficient designs.