By Topic

Physical yield improvement for SiGe Selective Epitaxial Growth fabrication process on nano scale pMOS strain engineering

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ming Mao Chu ; Eng. Sci. Dept., Nat. Cheng Kung Univ., Tainan, Taiwan ; June-Hua Chou

In the SiGe strain engineering on pMOS, the reactive ion etching (RIE) is using to prepare a Si recess, and then use epitaxial growth to form SiGe strain liner on both sides of poly gate. In the dense line CMOS, the shrunk Si recess dimension make it steeper and introduces the challenge to remove the post etch polymer residue. It is investigated that residual polymer on steep side wall of channel will prohibit the following selective epitaxial growth of SiGe (SEG) and directly impact the yield. An enhanced chemical process has proposed for surface preparation and the processes are explored to determine the clean efficiency of plasma modified polymer residue. The developed process is capable to eradicate residual polymer defect on both isolated and dense layout structure of 45 nm pMOS and resulted 3~10% physical yield improvement.

Published in:

Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE

Date of Conference:

2-5 June 2009