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Comprehensive Approach to High-Performance Server Chipset Debug

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2 Author(s)
Parulkar, I. ; Sun Microsyst., Santa Clara, CA, USA ; Turumella, B.

This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.

Published in:

Design & Test of Computers, IEEE  (Volume:26 ,  Issue: 3 )