A Low Power 12-Bit 20Msamples/s Pipelined ADC

A 12-bit 20 MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 mum mix-signal CMOS technology, the ADC dissipates 71 mW from a 5 V supply, and achieves a peak SNDR of 69.8 dB with a 0.5 MHz full-scale sine input at 20 MS/s.