By Topic

A Low Power 12-Bit 20Msamples/s Pipelined ADC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Cao Junmin ; Inst. of Microelectron., Peking Univ., Beijing, China ; Chen Zhongjian ; Lu Wengao ; Zhao Baoying

A 12-bit 20 MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 mum mix-signal CMOS technology, the ADC dissipates 71 mW from a 5 V supply, and achieves a peak SNDR of 69.8 dB with a 0.5 MHz full-scale sine input at 20 MS/s.

Published in:

2009 International Conference on Signal Processing Systems

Date of Conference:

15-17 May 2009