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Process variability has become a fundamental challenge in nanometer technologies. This trend is driven by Moore's law, which governs the exponential growth of transistors in ICs, the low-power requirements of mobile devices (i.e., Vdd < 1 V), and the shrinking geometries of advanced technologies reaching the sub-nanometer dimensions. Understanding process variability is therefore key to successfully designing ultra low-power multi-million gate SoCs. An all-digital on-chip process control-monitor (PCM) that measures process variability is described. It is implemented in a 65 nm dual-oxide triple-Vt bulk CMOS process and it measures 0.41 mm2.