By Topic

A low-power multi-core media co-processor for mobile application processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Nomura, S. ; Digital Media SoC Dept., Toshiba Corp., Kawasaki, Japan ; Tachibana, F. ; Fujita, T. ; Chen Kong Teh
more authors

A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65 nm CMOS technology consumes 620 mW in H.264 720p 60 fps decoding and 9.7 mW in MPEG-4 AAC decoding. In the maximum workload of H.264 decoding, a symmetrical parallelization achieves 7.5times performance enhancement by 8 cores. The shared L2 cache reduces the required rate of main memory access to 310 MB/s. In the minimum workload of AAC decoding, three low-power circuit techniques reduce 98% of leakage. On-chip regulators, which also work as power-gating switches, lower the supply voltage of processing cores. Embedded forward body-biasing circuit reduces Vt variations. A low-power and fast data-mapping F/F relaxes the timing constraint, which enables a reduction in the number of low-Vt transistors.

Published in:

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date of Conference:

18-20 May 2009