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In DSM era, digital circuits can contain millions placeable elements, and the complexity and the size of circuits have grown exponentially. For reducing the circuit sizes, clustering algorithm have become popular, so that the placement process can be performed faster and with higher quality. In this paper, we proposed a novel basic-pre-clustering clustering algorithm called Cell Merge which can reduce effectively the circuit size. The algorithm has proven a linear-time complexity of O(n), where n is the number of nets in a circuit. The numerical experiments on ISPD02 IBM-MS mixed-size benchmark suite for placement show that by applying Cell Merge as a processing step, the performance of state-of-the-art placer can be further improved.