By Topic

Through Silicon Via stress characterization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dao, T. ; Freescale Semicond., Austin, TX, USA ; Triyoso, D.H. ; Petras, M. ; Canonico, Michael

In this paper, we will present Micro Raman stress data of Through Silicon Vias (TSV) with different shapes and sizes & spacing, and discuss design considerations.

Published in:

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date of Conference:

18-20 May 2009