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Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

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4 Author(s)
Chang-Tzu Wang ; Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Ming-Dou Ker ; Tien-Hao Tang ; Kuan-Cheng Su

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7 kV human-body-model (HBM) and 325 V machine model (MM) ESD tests which occupying an silicon area of only 49 mum times 21 mum and consuming a very low standby leakage current of 96 nA at room temperature.

Published in:

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date of Conference:

18-20 May 2009

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