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Implementation and evaluation of fine-grain run-time power gating for a multiplier

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7 Author(s)
Usami, K. ; Shibaura Inst. of Technol., Tokyo, Japan ; Nakata, M. ; Shirai, T. ; Takeda, S.
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In a 32btimes32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32btimes32b multiplier and implementing in a commercial 90 nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25degC to 10 cycles at 65degC and to 3 cycles at 100degC at 100 MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65degC and by 39% at 100degC over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25degC. The ground bounce at the wakeup was effectively suppressed to 91 mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44 ns.

Published in:

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date of Conference:

18-20 May 2009