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A three dimensional low noise amplifier using post-processed transmission lines on a 130 nm CMOS technology is presented. A 15 nm thick low-k and low-loss Parylene-N layer is used to elevate transmission lines from the lossy Si substrate. This reduces the attenuation per unit length of the transmission lines by about 60%, while preserves CMOS chip area (in this specific design) by approximately 25% that is otherwise dedicated to these lines. The 3D amplifier measures a gain of 13 dB at 2 GHz with 3 dB bandwidth of 500 MHz, noise figure of 3.3 dB and output 1 dB compression point of +4.6 dBm. With a simple room temperature CMOS compatible post-fabrication process, smaller chips with better performances are achieved. It is also shown that accurate simulation of a 3D circuit is attained by considering various parasitic effects that exist in this type of implementation.