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Combined Nanoscale and Device-Level Degradation Analysis of \hbox {SiO}_{2} Layers of MOS Nonvolatile Memory Devices

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8 Author(s)
Lanza, M. ; Dept. of Electron. Eng., Univ. Autonoma de Barcelona, Barcelona, Spain ; Porti, M. ; Nafria, M. ; Aymerich, X.
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In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick SiO2 layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements.

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Device and Materials Reliability, IEEE Transactions on  (Volume:9 ,  Issue: 4 )