Cart (Loading....) | Create Account
Close category search window
 

Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD- \hbox {Al}_{2}\hbox {O}_{3} Gate Dielectric

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Cheng, Chao-Ching ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chien, Chao-Hsin ; Luo, Guang-Li ; Ching-Lun Lin
more authors

In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+-n and n+-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10-2 and 10-4 A ldr cm-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al2O3/Ge interface states to 8 times 1011 cm-2 ldr eV-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm2 ldr V-1 ldr s-1 and > 103, respectively, for the p-FET (W/L = 100 mum/4 mum), while these values were less than 100 cm2 ldr V-1 ldr s-1 and ca. 103, respectively, for the n-FET (W/L = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.

Published in:

Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 8 )

Date of Publication:

Aug. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.