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A nonlinear power distribution network model for characterizing the immunity of integrated circuits (ICs) to electrical fast transients (EFTs) is proposed and validated. The model includes electrostatic discharge (ESD) protection diodes and passive impedances between power domains. Model parameters are based on external measurements using a vector network analyzer and curve tracer. Impedance is measured between pins while the IC is biased and operating, and is used to determine individual elements of the network model. Inclusion of active power-clamp circuitry is also explored. The model is able to successfully predict pin currents and voltages during EFTs on the power pin when the IC is operating or turned off and when the ESD power clamp is either activated or not activated. This model might be used to evaluate the immunity of the IC in a variety of systems and to better understand why failures occur within the IC and how to fix them.