Referenced Items are not available for this document.
We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.
Published in:
Electron Device Letters, IEEE
(Volume:30
,
Issue:
8
)
Date of Publication: Aug. 2009
- Page(s):
- 852 - 854
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 10793176
- Digital Object Identifier :
- 10.1109/LED.2009.2024014
- Product Type:
- Journals & Magazines
- Date of Publication :
- 10 July 2009
- Date of Current Version :
- 24 July 2009
- Issue Date :
- Aug. 2009
- Sponsored by :
- IEEE Electron Devices Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
