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In this paper, we present a systematic study of the role of metal/semiconductor nanowire (NW) contact in back-gated Ge and Si NW Schottky-barrier (SB) FETs. Our results show that the performance of such devices is largely dominated by the carrier injection efficiency at the source contact, which, in turn, is controlled by metal contact depth and gate bias. Using low-temperature annealing of back-gated Ge and Si NW SB FETs with nickel (Ni) contacts as source and drain, we monitor the evolution of the device current as the contact metal progressively diffuses into the NWs. The drain current, which is measured at a given gate and drain bias, first increases as the contact metal diffuses into the NW, reaches a maximum, and subsequently decreases. These results can be explained by the interplay between carrier injection efficiency through the metal/NW SB, which increases with the metal contact depth, and the number of available states in the NW between contact and the bottom oxide, which decreases with the metal contact depth.