By Topic

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Mizuochi, T. ; Mitsubishi Electr. Corp., Kamakura, Japan ; Konishi, Y. ; Miyata, Y. ; Inoue, T.
more authors

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative decoding for an input bit-error rate of 8.9 times 10-3 at 31.3 Gb/s.

Published in:

Photonics Technology Letters, IEEE  (Volume:21 ,  Issue: 18 )