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Dynamic CPU cache management under the loop model

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3 Author(s)
Jaouhar, C. ; Dept. of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL, USA ; Mahgoub, I. ; Hewett, R.

Concerns cache designs using replacement strategies to provide the high performance required by fast CPUs. We propose a new replacement technique that uses some heuristic to detect loop structures in the reference patterns. Initially, the proposed technique uses the least recently used (LRU) strategy. Once a loop has been detected, all the references, which would result in poor performance if they were to be cached, will be dynamically excluded from being stored in the cache. The LRU strategy will resume as soon as the end of the loop has been detected. We have also developed a simulation program to compare the performance of this scheme to that of other related ones so as to demonstrate its effectiveness. The results show our scheme outperforms the others when the system references are loop dominated

Published in:

Southcon/95. Conference Record

Date of Conference:

7-9 Mar 1995

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