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Using hardware transactional memory for data race detection

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5 Author(s)
Gupta, S. ; Dept. of EE & CS, Univ. of Michigan, Ann Arbor, MI, USA ; Sultan, F. ; Cadambi, S. ; Ivancic, F.
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Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable. Dependable multithreaded software will have to rely on the ability to dynamically detect non-deterministic and notoriously hard to reproduce synchronization bugs manifested through data races. Previous solutions to dynamic data race detection have required specialized hardware, at additional power, design and area costs. We propose RaceTM, a novel approach to data race detection that exploits hardware that will likely be present in future multiprocessors, albeit for a different purpose. In particular, we show how emerging hardware support for transactional memory can be leveraged to aid data race detection. We propose the concept of lightweight debug transactions that exploit the conflict detection mechanisms of transactional memory systems to perform data race detection. We present a proof-of-concept simulation prototype, and evaluate it on data races injected into applications from the SPLASH-2 suite. Our experiments show that this technique is effective at discovering data races and has low performance overhead.

Published in:

Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on

Date of Conference:

23-29 May 2009

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