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Optimizing wiring space in slicing floorplans

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2 Author(s)
Mowchenko, J.T. ; Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada ; Yang, Y.

This paper addresses the problem of minimizing wiring space in an existing slicing floorplan. Wiring space is measured in terms of net density, and the existing floorplan is adjusted only by interchanging sibling rectangles and by mirroring circuit modules. An exact branch and bound algorithm and a heuristic are given for this problem. Experiments show that both algorithms are effective in reducing wiring space in routed layouts

Published in:

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Date of Conference:

16-18 Mar 1995