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Bus minimization and scheduling of multi-chip systems

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2 Author(s)
Sheliga, M. ; Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA ; Sha, E.H.-M.

This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms

Published in:

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Date of Conference:

16-18 Mar 1995