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This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.