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The development of future nanoscale CMOS circuits, characterized by lower supply voltages and smaller dimensions, raises the question of logic stability of such devices with respect to electrical noise. This paper presents a theoretical framework that can be used to investigate the thermal noise probability distributions for equilibrium and nonequilibrium logic states of CMOS flip-flops operated at subthreshold voltages. Representing the investigated system as a 2-D queue, a symbolic solution is proposed for the moments of the probability density function for large queues where Monte Carlo and eigenvector methods cannot be used. The theoretical results are used to calculate the mean time to failure of flip-flops built in a current 45-nm silicon-on-insulator technology modeled in the subthreshold regime including parasitics. As a predictive tool, the framework is used to investigate the reliability of flip-flops built in a future technology described in the International Technology Roadmap for Semiconductors. Monte Carlo simulations and explicit symbolic calculations are used to validate the theoretical model and its predictions.