Skip to Main Content
Critical defects, i.e., faults, inevitably occur during semiconductor fabrication, and they significantly reduce both manufacturing yield and product reliability. To decrease the effects of the defects, several fault-tolerance methods, such as the redundancy technique and the error correcting code (ECC), have been successfully applied to memory integrated circuits. In the semiconductor business, accurate estimation of yield and reliability is very important for determining the chip architecture as well as the production plan. However, a simple conjunction of previous fault-tolerant yield models tends to underestimate the manufacturing yield if several fault-tolerance techniques are employed simultaneously. This paper concentrates on developing and verifying an accurate yield model which can be applied successfully in such situations. The proposed conjunction model has been derived from the probability of remaining redundancies and the average number of defects after repairing the defects with the remaining redundancies. The validity of the conjunction yield model is verified by a Monte Carlo simulation.