By Topic

A comparison study of Silicon Nanowire Transistor with Schottky-Barrier source/drain and doped source/drain

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Zhaoyi Kang ; Dept. of Microelectron., Peking Univ., Beijing, China ; Liangliang Zhang ; Runsheng Wang ; Ru Huang

Schottky barrier (SB) S/D nanowire transistor (SB-NWT) is considered to be one of the candidates for future CMOS technology due to the combination of the advantages both from silicon nanowire (NW) transistor (SNWT) and metal S/D. However, previous studies, both simulations and experiments, show that the electrostatic properties (EPs) of SB-NWTs are not promising. In this paper, SB-NWTs is comprehensively studied in comparison with SNWTs. The SB impact is found to be responsible for the degraded EPs and contributes to unexpectedly large linear region resistance (Rlin). Several approaches to minimize the SB impact are studied and limitations of the approaches are investigated in comparison with SNWTs. Whether SB-NWTs can show better performance than SNWTs will be further discussed.

Published in:

VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on

Date of Conference:

27-29 April 2009