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We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/mum at Vd = 1.0 V and ion = 1154 muA/mum was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 muA/mum for Ioff = 100 nA/mum at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective ldquodualrdquo embedded stressor.