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Efficient Data Access Management for FPGA-Based Image Processing SoCs

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3 Author(s)
Larabi, Z. ; TELECOM ParisTech, Inst. TELECOM, Paris, France ; Mathieu, Y. ; Mancini, S.

In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-based image and signal processing systems on chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define the cachepsilas practical implementation based on the application and system parameters. Complexity and performance for selected image processing algorithms like jumping snake and 2D back-projection are measured and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.

Published in:

Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on

Date of Conference:

23-26 June 2009