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System-level development and verification framework for high-performance system accelerator

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4 Author(s)
Chen-Chieh Wang ; Inst. of Comput. & Commun. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Ro-Pun Wong ; Jing-Wun Lin ; Chung-Ho Chen

In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.

Published in:

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Date of Conference:

28-30 April 2009