By Topic

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Tong-Yu Hsieh ; Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101 ; Kuen-Jong Lee ; Melvin A. Breuer

In many multimedia applications, some faults induce errors that are user-imperceptible and thus are acceptable. By not testing for these faults, the effective yield can be significantly increased based on the principle of error-tolerance. However, studies have shown that test patterns generated by a conventional ATPG procedure targeting only unacceptable faults also detect many acceptable faults, resulting in a significant degradation in achievable yield improvement. In this paper we present a multi-phase test technique that can perfectly prevent this over-detection problem. Solid theoretical derivations are provided to validate the effectiveness of this technique. Compared with previous work, only a much smaller number of test patterns are required and thus the required test cost can be much lower. Experimental results on benchmark circuits illustrate the high efficiency of this novel technique.

Published in:

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Date of Conference:

28-30 April 2009