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An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1lesMles7, and 1lesNles8). It has been fabricated in a 0.18 um CMOS process. The measured rms jitter of the output clock is 3 ps when the input clock is 133 MHz, M is 7, and N is 1 and consumes 53 mW from a supply of 1.8 V. The core area of this clock generator is 0.26 mm2.